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ltc3446 1 3446ff typical a pplica t ion fea t ures a pplica t ions descrip t ion monolithic buck regulator with dual vldo regulators the ltc ? 3446 combines a synchronous buck dc/dc con- verter with two very low dropout (vldo) linear regulators to provide up to three stepped-down output voltages from a single input voltage. the input voltage range is ideally suited for li-ion battery-powered applications, as well as powering low voltage logic from 5v or 3.3v rails. the output voltage range extends down to 0.4v for the vldo regulators and 0.8v for the buck. the 1a synchronous buck converter provides the main output with high effciency, typically 85%. the two 300ma vldo regulators can run off the main output to provide two additional lower voltage outputs. a built-in supply monitor provides a power good indication. the buck converter switches at 2.25mhz, allowing the use of small surface mount inductors and capacitors. constant frequency current mode operation produces controlled output spectrum and fast transient response. a mode- select pin allows automatic burst mode operation to be enabled for higher effciency at light load, or disabled for lower noise operation down to very light loads. the two vldo regulators are stable with ceramic output capacitors as small as 1f. l , lt, ltc, ltm and burst mode are registered trademarks and vldo, hot swap, powerpath and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6611131, 6304066, 6498466, 6580258. buck effciency vs buck load current n high effciency triple step-down outputs from a single input supply n 1a synchronous buck regulator provides main step-down output and powers two 300ma vldo? linear regulators n output voltages as low as 400mv (vldo outputs) n power good output n input voltage range: 2.7v to 5.5v n independent enable pin for each supply n low (140a typ) no-load quiescent current with all outputs enabled n constant frequency current mode operation n 2.25mhz switching frequency uses small inductors n defeatable automatic burst mode ? operation for high effciency at light loads n 1.5% reference accuracy n overtemperature protection n thermally enhanced 4mm 3mm 14-pin dfn package n low power handheld devices n low voltage and multivoltage power for digital logic, i/o, fpgas, cplds, asics and cpus v in 59k l1 1.8h 47.5k sw buckfb lv in ltc3446 gnd 22f x7r 1000pf digital control 22f x7r v out 1.8v 400ma max 110k 40.2k 2.2f x7r v out 1.5v 300ma max v in 2.9v to 5.5v lv out1 pgood modesel enbuck enldo1 enldo2 lv fb1 80.6k 40.2k 2.2f x7r l1: toko a960aw-1r8m 3446 ta01 v out 1.2v 300ma max lv out2 3.3k i th lv fb2 load current (ma) 1 40 efficiency (%) 50 60 70 80 100 10 100 3446 ta01b 1000 90 v in = 2.7v v in = 3.6v v in = 4.2v burst mode operation pwm mode
ltc3446 2 3446ff p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , lv in to gnd ......................................... C 0.3v to 6v modesel, enbuck, enldo1, enldo2 to gnd .......................................... C0.3v to 6v buckfb to gnd .......................................... C0.3v to 6v lv fb1 , lv fb2 to gnd .................................... C0.3v to 6v i th to gnd ..... C0.3v to the lesser of (v in + 0.3v) or 3v sw to gnd ...... C0.3v to the lesser of (v in + 0.3v) or 6v lv out1 , lv out2 to gnd .......... C0.3v to the lesser of (l v in + 0.3v) or 6v pgood to gnd ............................................ C0.3v to 6v lv out1 , lv out2 short-circuit to gnd duration ............................................... indefnite operating junction t emperature range (note 2) .................................................. C40c to 125c storage t emperature range .................. C65c to 150c (note 1) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sw enbuck buckfb enldo1 lv fb1 lv fb2 enldo2 modesel v in i th pgood lv out1 lv in lv out2 top view de package 14-lead (4mm 3mm) plastic dfn 15 t jmax = 125c, v ja = 43c/w exposed pad (pin 15) is gnd, must be soldered to pcb or d er in f or m a t ion lead free finish tape and reel part marking * package description temperature range ltc3446ede#pbf ltc3446ede#trpbf 3446 14-lead (4mm w 3mm) plastic dfn C40c to 125c ltc3446ide#pbf ltc3446ide#trpbf 3446 14-lead (4mm w 3mm) plastic dfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units v in input voltage range (note 3) 2.7 5.5 v v uvlo v in undervoltage lockout threshold v in undervoltage lockout hysteresis v in rising 2.37 10 2.5 30 v mv i q v in quiescent current (note 4) buck enabled only, not sleeping buck enabled only, sleeping one ldo enabled only all three outputs enabled, buck not sleeping all three outputs enabled, buck sleeping shutdown v buckfb = 0v, i sw = 0ma v buckfb = 1v, i sw = 0ma v lvin = 1.5v, 10a ldo output load v buckfb = 0v, i sw = 0ma, v lvin = 1.5v, 10a output load on each ldo v buckfb = 1v, i sw = 0ma, v lvin = 1.5v, 10a load on each ldo v enbuck = 0v, v enldo1 = 0v, v enldo2 = 0v 310 50 75 400 140 500 75 100 600 210 1 a a a a a a e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 3.6v unless otherwise specifed. (note 2)
ltc3446 3 3446ff e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 3.6v unless otherwise specifed. (note 2) symbol parameter conditions min typ max units v pg(thresh) pgood threshold (note 8) 8 10 % r pgood pgood output resistance pgood low, sinking 1ma 87 180 i pgood pgood hi-z leakage current v pgood = 6v 1 a synchronous buck converter i buckfb feedback current (note 5) 30 na v buckfb regulated feedback voltage (note 5) 0.788 0.800 0.812 v ?v buckfb feedback voltage line regulation v in = 2.7v to 5.5v (note 5) 0.3 0.5 mv/v i maxp maximum peak inductor current v buckfb = 0v, duty cycle < 35% 1.2 1.55 2.0 a i maxn nmos overcurrent limit 1.8 a feedback voltage load regulation (with respect to v ith ) v ith = 0.5v to 1v, v modesel = v in (note 5) 0.5 mv/v f osc oscillator frequency 1.8 2.25 2.7 mhz r pfet r ds(on) of p-channel fet i sw = 500ma 0.13 r nfet r ds(on) of n-channel fet i sw = C500ma 0.14 i lsw sw leakage v enbuck = 0v, v sw = 0v or 5.5v, v in = 5.5v 1 a v enbuck buck enable pin threshold 0.3 0.65 1 v i enbuck buck enable pin leakage current v enbuck = 5.5v, all other pins grounded 1 a v modesel mode select pin threshold 0.3 0.65 1 v i modesel mode select pin leakage current v modesel = 5.5v, all other pins grounded 1 a g m error amplifer transconductance v ith = 0.6v 450 700 950 a/v each vldo: v in = 3.6v, v lvin = 1.5v, v lvout = 1.2v, unless otherwise specifed v lvin lv in pin operating voltage (note 6) 0.9 5.5 v i lvin lv in pin operating current i out = 10a 3 20 a lv in shutdown current v enldo = 0v 1.5 2 a v lvfb feedback pin regulation voltage (note 7) 1ma i out 300ma, 1.5v v lvin 5.5v 0.395 0.392 0.400 0.400 0.405 0.408 v v i lvfb feedback pin input current v lvfb at regulation 2 10 na i lvout(max) continuous output current 300 ma short-circuit output current 760 ma v enldox ldo enable pin threshold 0.3 0.65 1 v i enldox ldo enable pin leakage current v enldox = 5.5v, all other pins grounded 1 a output voltage load regulation (referred to the lv fb pin) ?i out = 1ma to 300ma C1 mv/a l vfb line regulation (with respect to the l vin pin) v lvin = 1.5v to 5.5v, v in = 3.6v, v lvout = 1.2v, i out = 1ma 7.5 v/v l vfb line regulation (with respect to the v in pin) v lvin = 1.5v, v in = 2.7v to 5.5v, v lvout = 1.2v, i out = 1ma 0.44 mv/v v do lv in C lv out dropout voltage v in = 2.8v, v lvin = 1.5v, v lvfb = 0.37v, i out = 300ma (note 9) 68 175 mv v in to lv out headroom required for regulation (note 3) i lvout = 300ma l 1.4 v
ltc3446 4 3446ff elec t rical charac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3446 is tested under pulsed load conditions such that t j t a . the ltc3446e is guaranteed to meet performance specifcations from 0c to 85c operating junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design characterization and correlation with statistical process controls. the ltc3446i is guaranteed to meet performance specifcations over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifcations is determined by specifc operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3: minimum operating v in voltage required for the vldo regulators to stay in regulation is: v in lv out(max) + 1.4v and v in 2.7v note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: the ltc3446 is tested in a feedback loop that connects the buckfb pin to the output of the buck converters error amplifer (i.e., the i th pin). note 6: minimum operating lv in voltage required for the vldo regulators to stay in regulation is: lv in l vout(max) + 100mv and lv in 0.9v note 7: operating conditions are limited by maximum junction temperature. the regulated output voltage specifcation will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited. note 8: pgood assertion indicates that the feedback voltages of all enabled supplies are within the specifed percentage of their target values. note 9: dropout voltage in the dfn package is assured by design, characterization and statistical process control. buck regulated feedback voltage vs temperature ldo1 regulated feedback voltage vs temperature ldo2 regulated feedback voltage vs temperature temperature (c) ?50 v buckfb (mv) 800 802 804 110 3446 g01 798 796 792 ?10 30 70 ?30 130 10 50 90 794 808 806 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v temperature (c) ?50 v lvfb1 (mv) 400 402 404 110 3446 g02 398 396 392 ?10 30 70 ?30 130 10 50 90 394 408 406 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v temperature (c) ?50 v lvfb2 (mv) 400 402 404 110 3446 g03 398 396 392 ?10 30 70 ?30 130 10 50 90 394 408 406 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v typical p er f or m ance c harac t eris t ics
ltc3446 5 3446ff typical p er f or m ance c harac t eris t ics undervoltage lockout threshold vs temperature maximum peak inductor current oscillator frequency vs temperature temperature (c) ?50 2.00 v in (v) 2.05 2.15 2.20 2.25 2.50 2.35 ?10 30 50 130 3446 g04 2.10 2.40 2.45 2.30 ?30 10 70 90 110 uvlo rising uvlo falling temperature (c) ?50 current (a) 2.0 2.4 2.3 2.2 2.1 1.9 2.5 10 50 130 3446 g05 1.6 1.8 1.7 1.2 1.1 1.4 1.5 1.3 1.0 ?30 ?10 30 70 11090 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v temperature (c) ?50 2.00 oscillator frequency (mhz) 2.05 2.15 2.20 2.25 2.50 2.35 ?10 30 50 130 3446 g06 2.10 2.40 2.45 2.30 ?30 10 70 90 110 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v peak inductor current vs i th voltage vldo current limit vs lv in voltage vldo dropout voltage vs load current i th pin voltage (v) 0 peak inductor current (a) 0.8 1.2 2 3446 g07 0.4 0 0.5 1 1.5 0.25 0.75 1.25 1.75 1.6 v in = 3.6v v modesel = 3.6v 0.6 1.0 0.2 1.4 lv in pin voltage (v) 0.00 0 vldo current limit (ma) 200 600 800 1000 4.00 1800 3446 g08 400 2.00 1.00 5.00 3.00 6.00 1200 1400 1600 v in = 3.6v lv out = 0v pulsed measurement, t j t a 27c load current (ma) 0 0 dropout voltage (mv) 20 40 60 50 100 150 200 3446 g09 250 80 100 10 30 50 70 90 300 ?45c 27c 90c 130c v in = 2.8v lv out = 1.2v v in bias current vs vldo load current lv in no-load operating current enable/modesel thresholds vldo output current (ma) 0 0 v in current (a) 50 150 200 250 200 450 3446 g10 100 100 50 250 150 300 300 350 400 ?45c 27c 90c 130c v in = 3.6v lv in = 1.5v lv out = 1.2v only one vldo enabled lv in pin voltage (v) 0 0 lv in current (a) 4 8 12 1 2 3 4 3446 g11 5 16 20 2 6 10 14 18 6 v in = 5v both vldos on and regulating 0.8v ?45c 27c 90c 130c v in (v) 2.5 0 enable/modesel threshold (mv) 200 400 600 3 3.5 4 4.5 3446 g12 5 800 1000 100 300 500 700 900 5.5 ?45c 27c 90c 130c
ltc3446 6 3446ff typical p er f or m ance c harac t eris t ics buck pmos switch on-resistance buck nmos switch on-resistance buck transient response with burst mode defeated buck transient response with burst mode enabled vldo transient response vldo rejection of buck dc/dc burst mode ripple temperature (c) ?45 pmos resistance (m) 160 180 200 30 80 3446 g13 140 120 ?20 5 55 105 130 100 80 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v temperature (c) ?45 nmos resistance (m) 160 180 200 30 80 3446 g14 140 120 ?20 5 55 105 130 100 80 v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.5v 100s/div 3446 g15 buck output voltage 50mv/div ac-coupled load current 500ma 50ma front page application circuit 100s/div 3446 g16 buck output voltage 50mv/div ac-coupled load current 500ma 50ma front page application circuit 100s/div lv out = 1.5v or 1.2v front page application circuit 3446 g17 vldo output voltage 20mv/div ac-coupled load current 300ma 30ma v lvin = buck v out 20mv/div ac-coupled v lvin = buck v out = 1.8v v in = 4.2v v lvout = 1.5v i lvout = 50ma c lvout = 2.2f v lvout 10mv/div ac-coupled 2s/div 3446 g18
ltc3446 7 3446ff p in func t ions modesel (pin 1): chooses between burst mode operation and pulse-skipping operation at light loads. forcing this pin below 0.3v allows the buck converter to automatically enter burst mode operation at light loads. forcing this pin above 1v disallows entering burst mode operation; the buck converter will cycle skip at light loads. do not leave this pin foating. this is a mos gate input. v in (pin 2): input supply to the ltc3446. must be closely decoupled to gnd with a 10f or greater ceramic capacitor. i th (pin 3): buck error amplifer output and servo-loop compensation point. pgood (pin 4): supply monitor output, open-drain nmos. lv out1 (pin 5): output of the first vldo regulator. lv in (pin 6): input supply to the ltc3446s vldo circuits. bypass lv in to gnd with at least a 1f low esr ceramic capacitor. typical ltc3446 application circuits will connect this pin to the output of the buck converter but this is not required. the vldo regulators may be used independently of the buck converter. lv out2 (pin 7): output of the second vldo regulator. lv fb2 (pin 9): feedback pin for the second vldo regulator. an output divider should be connected from lv out2 to lv fb2 to set the desired lv out2 regulated output voltage. lv fb1 (pin 10): feedback pin for the first vldo regulator. an output divider should be connected from lv out1 to lv fb1 to set the desired lv out1 regulated output voltage. enldo1/enldo2 (pin 11/pin 8): enable pin for the first and second vldo regulators, respectively. forcing this pin above 1v enables the corresponding vldo regulator and forcing this pin below 0.3v shuts it down. each vldo regulator draws <1a of supply current in shutdown. do not leave this pin foating. this is a mos gate input. buckfb (pin 12): buck converters feedback pin. receives the feedback voltage from an external resistive divider across the output. external resistance from this pin to ground should be equal to or less than 50k. enbuck (pin 13): enable pin for the ltc3446s buck converter circuit. forcing this pin above 1v enables the buck converter and forcing this pin below 0.3v shuts down the converter. in shutdown, the buck converter draws <1a of supply current. do not leave this pin foating. this is a mos gate input. sw (pin 14): switch node connection to inductor. this pin connects to the drains of the internal main and syn - chronous power mosfet switches. gnd (exposed pad, pin 15): ground. the exposed pad is the only ground and must connect to the pcb ground for electrical contact and rated thermal performance.
ltc3446 8 3446ff b lock diagra m ? + ? + ? + ? + ? + ? + 2 14 + pmos current comparator burst comparator nmos overcurrent comparator reverse current comparator b bclamp v in slope compensation i th limit oscillator power good i th park 3 4 i th 0.8v v b 0.4v voltage reference error amplifier logic sw 15 gnd exposed pad 6 lv in lv out1 lv fb1 6a v ldo1 soft-start v in 5 10 ? + lv out2 3446 bd lv fb2 6a v ldo2 soft-start v in 7 9 pgood 13 1 enbuck modesel 11 enldo1 8 enldo2 12 buckfb
ltc3446 9 3446ff the ltc3446 combines a constant frequency, current mode synchronous buck converter with two very low dropout (vldo) linear dc regulators to provide up to three high effciency, low voltage outputs from a single higher voltage input source. each output can be independently enabled and disabled. a power good circuit monitors all three sup - plies. the ltc3446 incorporates an undervoltage lockout circuit that shuts down the ic when the input voltage drops below about 2.4v to prevent unstable operation. synchronous buck operation a buck converter takes power from a high input voltage, v in , and delivers it at a lower output voltage, v out . the buck converter inside the ltc3446 achieves over 80% effcient power conversion under a wide range of v in , v out and load conditions, whereas a linear regulator is limited by physics to a maximum effciency of (v out /v in ) 100%. main control loop during normal operation, the internal oscillator produces a constant frequency 2.25mhz clock. the top power switch (p-channel mosfet) turns on at the beginning of a clock cycle. inductor current increases to a peak value which is set by the voltage on the i th pin. then the top switch turns off and the energy stored in the inductor fows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the voltage on the i th pin, which is the output of the error amplifer. this amplifer compares the buckfb pin to the 0.8v reference. when the load current increases, the buckfb voltage de- creases slightly below the reference. this decrease causes the error amplifer to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the enbuck pin to ground. overcurrent protection to help avert inductor current runaway in case the buck output is accidentally shorted to ground, the ltc3446 features a bottom switch nmos overcurrent limit, which works as follows. when the buck output is shorted to ground, inductor current will rise to its maximum peak level, i maxp , such that on every oscillator cycle the pmos top switch will turn on for only its minimum duty cycle, and the bottom switch nmos turns on for the remainder of the cycle. temporarily ignoring inductor, switch and parasitic resis - tance drops, which in most applications are designed to be small in order to maximize buck converter effciency, it is to frst order true that when the pmos is on, the v in supply voltage is placed across the inductor, increasing the inductor current, but when the nmos is on, there is no output voltage to be placed across the inductor to reduce its current. inductor current ratchets up each cycle and could lead to the destruction of the buck ic. the nmos overcurrent limit helps prevent this by sensing the current through the nmos bottom switch, and for as long as this current exceeds the overcurrent limit level, i maxn , it: 1. keeps the nmos on, allowing the tiny voltage drops from parasitic resistances to reduce the inductor current. 2. refuses to allow the pmos to turn on, preventing any additional energy from being fed into the system. low current operation the modesel pin controls the buck converter s behavior at light load currents to help optimize effciency, output ripple and noise. when the load is relatively light and modesel is grounded, the buck converter automatically switches into burst mode operation, which operates the pmos o pera t ion
ltc3446 10 3446ff opera t ion switch intermittently based on load demand rather than at a constant frequency. every switch cycle during burst mode operation delivers more energy than would occur in constant frequency operation, minimizing the switch- ing loss per unit of energy delivered. since the dominant power loss at light loads is gate charge switching loss in the power mosfets, operating in burst mode operation can dramatically improve light load effciency. the tradeoff is higher output ripple than in constant frequency opera- tion, as well as the presence of noise below the 2.25mhz clock frequency. if modesel were instead tied to v in , pulse skipping mode is selected. in this mode, the buck converter continues to switch at a constant frequency down to very light loads where it will eventually begin skipping pulses. because constant frequency operation is extended down to light loads, low output ripple is maintained and any coupled or radiated noise is at or higher than the clock frequency. the tradeoff is lower effciency compared to burst mode operation. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100%, which is known as the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage equal to the input voltage minus any voltage drop across the pmos switch and the external inductor. vldo linear regulator operation the two micropower, vldo (very low dropout) linear regulators in the ltc3446 operate from input voltages as low as 0.9v. each vldo regulator provides a high accuracy output that is capable of supplying 300ma of output cur - rent with a typical dropout voltage of only 70mv. a single ceramic capacitor as small as 1f is all that is required for output bypassing. a low reference voltage of 400mv allows the vldo regulators to be programmed to much lower voltages than available in common ldos. as shown in the block diagram, the v in input supplies the internal reference and biases the vldo circuitry while all output current comes directly from the lv in input for high effciency regulation. the low per-vldo quiescent supply currents i lvin = 4a, i vin = 80a drop to i lvin < 2a, i vin < 1a in shutdown, are well-suited to battery- powered systems. each vldo includes current limit protection. the fast transient response of the follower output stage overcomes the traditional tradeoff between dropout voltage, quiescent current and load transient response inherent in most ldo regulator architectures. overshoot detection circuitry is included to bring the output back into regulation when going from heavy to light output loads (load-dump handling). power good circuit operation the ltc3446 has a built-in supply monitor. the feedback voltage of each enabled supply is monitored by a window comparator to determine whether it is within 8% of its target value. if they all are, then the pgood pin becomes high impedance. if no supply is enabled, or if any enabled supply is more than 8% away from its target, then the pgood pin is driven to ground by an internal open-drain nmos. the pgood pin may be connected through a pull-up resistor to a supply voltage of up to 5.5v, independent of the v in pin voltage.
ltc3446 11 3446ff applica t ions in f or m a t ion a general ltc3446 application circuit is shown in figure 1. external component selection is driven by output voltage and load requirements. the following text is divided into two sections: the frst covers buck regulator design and the second covers use of the linear vldo regulators. buck regulator design buck regulator design begins with the selection of the l1 inductor based on desired ripple current. once l1 is chosen, c in and c outb can be selected based on output voltage ripple requirements. output voltage is programmed through r1 and r2, and loop response can be optimized by choice of r ith and c ith . inductor selection although the inductor does not infuence the operat- ing frequency, the inductor value has a direct effect on ripple current. the inductor ripple current ?i l decreases with higher inductance and increases with higher v in or v outb : ? i l = v outb f o ? l ? 1 ? v outb v in ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is ?i l = 0.3 ? i maxp , where i maxp is the peak switch current limit. the largest ripple current ?i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a specifed maximum, the inductor value should be chosen according to the following equation: l = v outb f o ? ? i l ? 1 ? v outb v in(max) ? ? ? ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in effciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. figure 1. general ltc3446 application circuit v in r2 l1 r1 sw buckfb lv in ltc3446 gnd c in c ith digital control c outb c f opt d1 opt v outb r4 r3 c out1 v out1 v in 2.7v to 5.5v lv out1 pgood modesel enbuck enldo1 enldo2 lv fb1 r6 r5 c out2 3446 f01 v out2 lv out2 r th i th lv fb2
ltc3446 12 3446ff applica t ions in f or m a t ion inductor core selection different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated feld/emi requirements than on what the ltc3446 requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3446 applications. table 1. representative surface mount inductors manu- facturer part number value max dc current dcr height toko a914byw-2r2m- d52lc 2.2h 2.05a 49m 2mm toko a915ay-2rom- d53lc 2h 3.3a 22m 3mm coilcraft d01608c-222 2.2h 2.3a 70m 3mm coilcraft lp01704-222m 2.2h 2.4a 120m 1mm sumida cdrh4d282r2 2.2h 2.04a 23m 3mm sumida cdc5d232r2 2.2h 2.16a 30m 2.5mm taiyo yuden n06db2r2m 2.2h 3.2a 29m 3.2mm taiyo yuden n05db2r2m 2.2h 2.9a 32m 2.8mm murata lqn6c2r2m04 2.2h 3.2a 24m 5mm wrth 744042001 1h 2.6a 20m 2mm catch diode selection although unnecessary in most applications, a small improvement in effciency can be obtained in a few ap- plications by including the optional diode d1 shown in figure 1, which conducts when the synchronous switch is off. when using burst mode operation or pulse skip mode, the synchronous switch is turned off at a low current and the remaining current will be carried by the optional diode. it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. the main problem with schottky diodes is that their parasitic capacitance reduces the effciency, usually negating the possible benefts for ltc3446 circuits. another problem that a schottky diode can introduce is higher leakage current at high temperatures, which could reduce the low current effciency. remember to keep lead lengths short and observe proper grounding to avoid ringing and increased dissipation when using a catch diode. input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v outb /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms i max v outb (v in ? v outb ) v in where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur - rent, i max = i maxp C ?i l /2. this formula has a maximum at v in = 2v outb , where i rms = i out /2. this simple worst case is commonly used to design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple cur - rent ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution.
ltc3446 13 3446ff applica t ions in f or m a t ion output capacitor (c outb ) selection the selection of c outb is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satisfed, the capacitance is adequate for fltering. the output ripple (?v outb ) is determined by: ? v outb ? i l esr + 1 8f o c outb ? ? ? ? ? ? ? ? where f = 2.25mhz, c outb = output capacitance and ?i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. once the esr requirements for c outb have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr(size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap, offer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but have a larger esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, avalable in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signifcantly larger esr, and are often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have the lowest esr and cost but also have the lowest capacitance density, a high voltage and temperature coeffcient and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to signifcant ringing. other capacitor types include the panasonic specialty polymer (sp) capacitors. in most cases, 0.1f to 1f of ceramic capacitors should also be placed close to the ltc3446 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. these are tempting for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor esr gener - ates a loop zero at 5khz to 50khz that is instrumental in giving acceptable loop phase margin. ceramic capacitors remain capacitive to beyond 300khz and usually resonate with their esl before esr becomes effective. also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating tem- perature range. to minimize their large temperature and voltage coeffcients, only x5r or x7r ceramic capacitors should be used. a good selection of ceramic capacitors is available from taiyo yuden, tdk and murata. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfll a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough
ltc3446 14 3446ff applica t ions in f or m a t ion to support the load. the time required for the feedback loop to respond is dependent on the compensation com- ponents and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the frst cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 3 times the linear drop of the frst cycle. thus, a good place to start is with the output capacitor size of approximately: c outb 2.5 ? i out f o ? v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10f ceramic capacitor is usually enough for these conditions. setting the buck converters output voltage the buck develops a 0.8v reference voltage between the feedback pin, buckfb, and the signal ground as shown in figure 1. the output voltage is set by a resistive divider according to the following formula: v outb 0.8v 1 + r2 r1 ? ? ? ? ? ? keep r1 at or less than 50k. great care should be taken to route the buckfb line away from noise sources, such as the inductor or the sw line. to improve high frequency loop response, a feed forward capacitor, c f , can be added as shown in figure 1. capacitor c f provides phase lead by creating a high frequency zero with r2, improving phase margin. buck converter shutdown the enbuck pin enables and shuts down the ltc3446s buck converter. do not leave this pin foating! tying enbuck to ground disables the buck converter. bringing enbuck more than 1v above ground enables the buck. checking buck converter transient response the opti-loop compensation allows the transient re - sponse to be optimized for a wide range of loads and output capacitors. the availability of the i th pin not only allows optimization of the control loop behavior but also provides a dc coupled and ac fltered closed-loop response test point. the dc step, rise time and settling at this test point truly refects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the front page typical application circuit will provide an adequate starting point for most applications. the series r-c flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v outb im- mediately shifts by an amount equal to ? i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c outb generating a feedback error signal used by the regulator to return v outb to its steady-state value. during this recovery time, v outb can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with r and the bandwidth of the loop increases with decreasing c.
ltc3446 15 3446ff applica t ions in f or m a t ion if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage v in drops toward v out , the load step capability does decrease due to the decreasing voltage across the inductor. applications that require large load step capabil - ity near dropout should use a different topology such as sepic, zeta or single inductor, positive buck/boost. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharged input capacitors are effectively put in paral- lel with c outb , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap controller is designed specifcally for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3446 circuits: 1) ltc3446 v in current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (<0.1%) loss that increases with v in , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfet s. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (qt + qb), where qt and qb are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, rl. in continuous mode, the average output current fowing through inductor l is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1 C dc) 4) other hidden losses such as copper trace and internal battery resistances can account for additional effciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching fre - quency. other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss.
ltc3446 16 3446ff applica t ions in f or m a t ion vldo linear regulator design adjustable output voltage each vldo regulators output voltage is set by the ratio of two external resistors as shown in figure 2. the vldo regulator servos the output to maintain the lv fb pin voltage at 0.4v (referenced to ground). thus the current in r1 is equal to 0.4v/r1. for good transient response, stability and accuracy, the current in r1 should be at least 8a, thus the value of r1 should be no greater than 50k. the current in r2 is the current in r1 plus the lv fb pin bias current. since the lv fb pin bias current is typically <10na, it can be ignored in the output voltage calculation. the output voltage can be calculated using the formula in figure 2. note that in shutdown, the output is turned off and the divider current will be zero once c out is discharged. each vldo regulator operates at a relatively high gain of C0.7v/ma referred to its lv fb input. thus a load current change of 1ma to 300ma produces a C0.2mv drop at the lv fb input. to calculate the change referred to the output, simply multiply by the gain of the feedback network (i.e., 1 + r2/r1). for example, to program the output for 1.2v, choose r2/r1 = 2. in this example, an output current change of 1ma to 300ma produces C0.2mv ? (1 + 2) = 0.6mv drop at the output. because the lv fb pins are relatively high impedance (de- pending on the resistor dividers used), stray capacitance at these pins should be minimized (<10pf) to prevent phase shift in the error amplifer loop. additionally, special attention should be given to any stray capacitances that can couple external signals onto the lv fb pins producing undesirable output ripple. for optimum performance, connect each lv fb pin to its resistor divider with a short pcb trace and minimize all other stray capacitance to the lv fb pin. vldo regulator output capacitance and transient response the vldo regulators are designed to be stable with a wide range of ceramic output capacitors. the esr of the output capacitor affects stability, most notably with small capacitors. a minimum output capacitor of 1f with an esr of 0.05 or less is recommended to ensure stability. the vldo regulators are micropower devices and output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. note that bypass capacitors used to decouple individual components powered by a vldo regulator will increase the effective output capaci- tor value. high esr tantalum and electrolytic capacitors may be used, but a low esr ceramic capacitor must be in parallel at the output. there is no minimum esr or maximum capacitor size requirements. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common di- electrics used are z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but exhibit large voltage and tem- perature coeffcients as shown in figures 3 and 4. when used with a 2v regulator, a 1f y5v capacitor can lose as much as 75% of its intial capacitance over the operating temperature range. the x5r and x7r dielectrics result figure 2. programming a vldo regulators output voltage r2 c out 3446 f02 v out = 0.4v 1+ r2 r1 r1 ( ) lv out lv fb gnd ltc3446
ltc3446 17 3446ff applica t ions in f or m a t ion in more stable characteristics and are usually more suit- able for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. in all cases, the output capacitance should never drop below 0.4f, or instability or degraded performance may occur. vldo output short-circuit protection the vldo regulators have built-in short-circuit limiting. during short-circuit conditions, internal circuitry automati - cally limits the output current to approximately 760ma. vldo regulator soft-start each vldo regulator includes a soft-start feature to prevent excessive current fow during start-up. when the vldo regulator is enabled, the soft-start circuitry gradually increases the vldo regulator reference voltage from 0v to 0.4v over a period of about 600s. there is a short 700s delay from the time the part is enabled until the ldo output starts to rise. figure 5 shows the start-up output waveform. figure 3. ceramic capacitor dc bias characteristics figure 4. ceramic capacitor temperature characteristics figure 5. vldo regulator output start-up dc bias voltage (v) change in value (%) 3446 f03 20 0 ?20 ?40 ?60 ?80 ?100 0 4 8 10 2 6 x5r y5v both capacitors are 1f, 10v, 0603 case size temperature (c) ?50 ?100 change in value (%) ?80 ?60 ?40 ?20 x5r y5v 20 ?25 0 25 50 3446 f04 75 0 both capacitors are 1f, 10v, 0603 case size 1.5v vldo output 1.2v vldo output 0.5v/div both vldo enables 5v/div v lvin = 1.8v v in = 3.6v front page application circuit with 10ma resistor loads on each vldo output 200s/div 3446 f05
ltc3446 18 3446ff p ackage descrip t ion de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc
ltc3446 19 3446ff information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number e 5/11 updated e-grade temperature grade to 125c, storage maximum temperature to 150c and ja to 43c/w. updated pgood output resistance maximum limit. added v in to lv out headroom specifcation. updated note 2. 2 3 3 4 f 5/11 updated parameter on v in to lv out specifcation 3 (revision history begins at rev e)
ltc3446 20 3446ff linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2006 lt 0511 rev f ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3023 dual, 2x100ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 40a, i sd < 1a, v out = adj, dfn, ms packages, low noise < 20v rms(p-p) , stable with 1f ceramic capacitors lt3024 dual, 100ma/500ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 60a, i sd < 1a, v out = adj, dfn, tssop packages, low noise < 20v rms(p-p) , stable with 1f ceramic capacitors ltc3025 300ma, micropower vldo linear regulator v in : 0.9v to 5.5v, v out(min) = 0.4v, 2.7v to 5.5v bias voltage required, v do = 45mv, i q = 50a, i sd < 1a, v out = adj, dfn packages, stable with 1f ceramic capacitors ltc3407 dual synchronous 600ma synchronous step-down dc/dc regulator 1.5mhz constant frequency current mode operation, v in from 2.5v to 5.5v, v out down to 0.6v, dfn, ms packages ltc3407-2 dual synchronous 800ma synchronous step-down dc/dc regulator, 2.25mhz 2.25mhz constant frequency current mode operation, v in from 2.5v to 5.5v, v out down to 0.6v, dfn, ms packages ltc3445 i 2 c controllable buck regulator with two ldos and and backup battery input 600ma, 1.5mhz current mode buck regulator, i 2 c programmable v out from 0.85v to 1.55v, two 50ma ldos, backup battery input with powerpath? control, qfn package ltc3555 high effciency usb power manager plus triple step-down dc/dc maximizes available power from usb port, bat-track?, instant on operation, 1.5a maximum charge current, 180m ideal diode with <50 option, 3.3v/25ma always-on ldo, three synchronous buck regulators (400ma/400ma/1a), 4mm w 5mm qfn28 package ltc3557 usb power manager with li-ion/polymer charger and triple synchrounous buck converter complete multifunction assp: linear power manager and three buck regulators, charge current programmable up to 1.5a from wall adapter input, thermal regulation, synchronous buck effciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/600ma, bat-track adaptive output control, 200m ideal diode, 4mm w 4mm qfn28 package ltc3559 linear usb li-ion battery charger with dual buck regulators charge current programmable up to 950ma, usb compatible, dual synchronous 400ma buck regulators, effciency >90%, 3mm w 3mm qfn16 package ltc3672b-1/ ltc3672b-2 fixed-output monolithic 400ma buck regulator with dual 150ma ldos in a 2mm w 2mm dfn >90% effciency, v in : 2.9v to 5.5v, i q = 260a, ltc3672b-1: buck = 1.8v, ldo1 = 1.2v, ldo2 = 2.8v ltc3672b-2: buck = 1.2v, ldo1 = 2.8v, ldo2 = 1.8v consult ltc factory for other voltage combinations ltc3700 step-down dc/dc controller with ldo regulator v in from 2.65v to 9.8v, constant frequency 550khz operation v in 59k l1 1.8h 47.5k sw buckfb lv in ltc3446 gnd 22f x7r 1000pf digital control 22f x7r v out 1.8v 400ma max 110k 40.2k 2.2f x7r v out 1.5v 300ma max v in 2.9v to 5.5v lv out1 pgood modesel enbuck enldo1 enldo2 lv fb1 80.6k 40.2k 2.2f x7r l1: toko a960aw-1r8m 3446 ta02 v out 1.2v 300ma max lv out2 3.3k i th lv fb2

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